1. Field of the Invention
The present invention generally relates to a technology for monitoring and testing the performance of a semiconductor circuit, and particularly relates to a method of monitoring and testing the circuit performance of a semiconductor circuit including a DLL (Delayed Locked Loop) circuit.
2. Description of the Related Art
In a semiconductor circuit, e.g. a CMOS LSI circuit, high-precision data processing is called for in a memory interface, such as a so-called DDR (Double-Data Rate), for which a high-speed and accurate data transfer is required. On the other hand, with a scaling down of the semiconductor circuit process in recent years, a trend for an increased amount of process variations is seen. As such process variations have a great impact on the performance of the LSI circuit such as the operation speed or the power consumption, monitoring the process (process monitoring) and screening the CMOS are performed for the purpose of ensuring that the amount of process variations of the LSI circuit is contained within a predetermined value.
In general, for the process monitoring and the product screening of the CMOS LSI, there are such techniques as measuring the amount of current at P and N channels of transistors configuring the LSI circuit concerned, and having embedded a ring oscillator in the LSI circuit so as to measure the oscillating frequency of this ring oscillator, etc.
FIG. 1A and FIG. 1B are diagrams for describing one exemplary prior-art process monitoring technique.
In FIG. 1A, a mask for an LSI-manufacturing method is manufactured in step S1, a wafer is manufactured in step S2, and the wafer is tested in step S3. Then the current amount of the semiconductor circuit manufactured is measured in step S4, and process-variation monitoring and product screening is performed in step S5. The circuit performance of the semiconductor circuit is analyzed from the current amount measured in step S4 so as to collate the analyzed performance with product-shipment standards for discarding an out-of-spec product.
Then, for within-spec products from step S5, assembling of the LSI circuit is performed in step S6, and for the assembled LSI circuit, product testing is performed in step S7. Then in step S8, frequency measurement is performed separately from the product testing in step S7. Here, as illustrated in FIG. 1B, the frequency of an oscillating signal obtained from the ring oscillator being pre-embedded in the LSI circuit (step S22) is measured. Then, based on the measurement results, the performance of the semiconductor circuit, or the process variation, is analyzed so as to collate the analyzed results with the product shipment standards for discarding out-of-spec products. Thus, the performance of a product is evaluated so as to determine whether the products can be shipped out (Step 9). If yes, the LSI circuit concerned is shipped in step S10.
Patent Document 1
JP2003-273728A
However, with such a prior-art technique, it is conceivable that the following problems arise:
1) The current amount (Ids) data at the P and the N channels of a transistor are often handled as data confidential to the manufacturer of the semiconductor so that often it is difficult for the user purchasing the LSI circuit to obtain the data.
2) It is difficult to derive from the current amount of the transistor the actual operating frequency range for each individual LSI circuit associated with the current amount.
3) For the technique of monitoring and screening by the ring oscillator that results in speed testing for monitoring the frequency, the testing is prone to measurement error, and moreover, when the oscillating frequency exceeds the measurement limit of a LSI tester at the user side, it is necessary to divide the output of the ring oscillator. Thus, when having divided the output of the ring oscillator, a decrease in the measurement precision cannot be avoided.